Embodiments of the present disclosure relate to a semiconductor device, and more particularly to a semiconductor device for improving a layout structure of a test circuit used in wafer testing.
Generally, integrated circuits (ICs) of semiconductor devices are manufactured as dies on a wafer, and are isolated from one another and then packaged.
To prevent unnecessary costs associated with packaging defective integrated circuits (ICs) from among all integrated circuits (ICs), it is preferable that all integrated circuits (ICs) undergo testing in a wafer state.
Such wafer testing may include a series of steps. In more detail, when a test mode is entered in response to a test mode signal at a high level, the wafer testing may include transmitting a test signal to a test circuit through a test pad by allowing a probe to contact the test pad which is isolated from a normal pad, and monitoring signals generated from the test circuit based on the test signal.
In accordance with the related art, after a test circuit used in wafer testing has been formed in a main circuit region of a semiconductor device, Electric Parameter Monitor (EPM) measurement of the test circuit is performed using pads or input/output (I/O) pins during a test mode of the semiconductor device.
However, guaranteeing a net die of semiconductor devices and guaranteeing Power Distribution Network (PDN) characteristics are becoming increasingly important. Additionally, the region occupied by a test circuit formed in each semiconductor device is gradually increasing in size.
In the case of using a pad configured to interconnect the inside and outside of each semiconductor device, the region occupied by the pad is large in size compared to a total region of the semiconductor device. However, since impact caused by physical contact of the probe occurs in wafer testing, no circuit is formed below the pad.